<!DOCTYPE html>
<html>
<!-- Created by GNU Texinfo 7.1, https://www.gnu.org/software/texinfo/ -->
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
<!-- Copyright © 1988-2023 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with the
Invariant Sections being "Funding Free Software", the Front-Cover
Texts being (a) (see below), and with the Back-Cover Texts being (b)
(see below).  A copy of the license is included in the section entitled
"GNU Free Documentation License".

(a) The FSF's Front-Cover Text is:

A GNU Manual

(b) The FSF's Back-Cover Text is:

You have freedom to copy and modify this GNU Manual, like GNU
     software.  Copies published by the Free Software Foundation raise
     funds for GNU development. -->
<title>Effective-Target Keywords (GNU Compiler Collection (GCC) Internals)</title>

<meta name="description" content="Effective-Target Keywords (GNU Compiler Collection (GCC) Internals)">
<meta name="keywords" content="Effective-Target Keywords (GNU Compiler Collection (GCC) Internals)">
<meta name="resource-type" content="document">
<meta name="distribution" content="global">
<meta name="Generator" content="makeinfo">
<meta name="viewport" content="width=device-width,initial-scale=1">

<link href="index.html" rel="start" title="Top">
<link href="Option-Index.html" rel="index" title="Option Index">
<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
<link href="Test-Directives.html" rel="up" title="Test Directives">
<link href="Add-Options.html" rel="next" title="Add Options">
<link href="Selectors.html" rel="prev" title="Selectors">
<style type="text/css">
<!--
a.copiable-link {visibility: hidden; text-decoration: none; line-height: 0em}
div.example {margin-left: 3.2em}
span:hover a.copiable-link {visibility: visible}
-->
</style>


</head>

<body lang="en">
<div class="subsection-level-extent" id="Effective_002dTarget-Keywords">
<div class="nav-panel">
<p>
Next: <a href="Add-Options.html" accesskey="n" rel="next">Features for <code class="code">dg-add-options</code></a>, Previous: <a href="Selectors.html" accesskey="p" rel="prev">Selecting targets to which a test applies</a>, Up: <a href="Test-Directives.html" accesskey="u" rel="up">Directives used within DejaGnu tests</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<h4 class="subsection" id="Keywords-describing-target-attributes"><span>7.2.3 Keywords describing target attributes<a class="copiable-link" href="#Keywords-describing-target-attributes"> &para;</a></span></h4>

<p>Effective-target keywords identify sets of targets that support
particular functionality.  They are used to limit tests to be run only
for particular targets, or to specify that particular sets of targets
are expected to fail some tests.
</p>
<p>Effective-target keywords are defined in <samp class="file">lib/target-supports.exp</samp> in
the GCC testsuite, with the exception of those that are documented as
being local to a particular test directory.
</p>
<p>The &lsquo;<samp class="samp">effective target</samp>&rsquo; takes into account all of the compiler options
with which the test will be compiled, including the multilib options.
By convention, keywords ending in <code class="code">_nocache</code> can also include options
specified for the particular test in an earlier <code class="code">dg-options</code> or
<code class="code">dg-add-options</code> directive.
</p>
<ul class="mini-toc">
<li><a href="#Endianness" accesskey="1">Endianness</a></li>
<li><a href="#Data-type-sizes" accesskey="2">Data type sizes</a></li>
<li><a href="#Fortran_002dspecific-attributes" accesskey="3">Fortran-specific attributes</a></li>
<li><a href="#Vector_002dspecific-attributes" accesskey="4">Vector-specific attributes</a></li>
<li><a href="#Thread-Local-Storage-attributes" accesskey="5">Thread Local Storage attributes</a></li>
<li><a href="#Decimal-floating-point-attributes" accesskey="6">Decimal floating point attributes</a></li>
<li><a href="#ARM_002dspecific-attributes" accesskey="7">ARM-specific attributes</a></li>
<li><a href="#AArch64_002dspecific-attributes" accesskey="8">AArch64-specific attributes</a></li>
<li><a href="#MIPS_002dspecific-attributes" accesskey="9">MIPS-specific attributes</a></li>
<li><a href="#MSP430_002dspecific-attributes">MSP430-specific attributes</a></li>
<li><a href="#PowerPC_002dspecific-attributes">PowerPC-specific attributes</a></li>
<li><a href="#RISC_002dV-specific-attributes">RISC-V specific attributes</a></li>
<li><a href="#Other-hardware-attributes">Other hardware attributes</a></li>
<li><a href="#Environment-attributes">Environment attributes</a></li>
<li><a href="#Other-attributes">Other attributes</a></li>
<li><a href="#Local-to-tests-in-gcc_002etarget_002fi386">Local to tests in <code class="code">gcc.target/i386</code></a></li>
<li><a href="#Local-to-tests-in-gcc_002etest_002dframework">Local to tests in <code class="code">gcc.test-framework</code></a></li>
</ul>
<div class="subsubsection-level-extent" id="Endianness">
<h4 class="subsubsection"><span>7.2.3.1 Endianness<a class="copiable-link" href="#Endianness"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">be</code></dt>
<dd><p>Target uses big-endian memory order for multi-byte and multi-word data.
</p>
</dd>
<dt><code class="code">le</code></dt>
<dd><p>Target uses little-endian memory order for multi-byte and multi-word data.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Data-type-sizes">
<h4 class="subsubsection"><span>7.2.3.2 Data type sizes<a class="copiable-link" href="#Data-type-sizes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">ilp32</code></dt>
<dd><p>Target has 32-bit <code class="code">int</code>, <code class="code">long</code>, and pointers.
</p>
</dd>
<dt><code class="code">lp64</code></dt>
<dd><p>Target has 32-bit <code class="code">int</code>, 64-bit <code class="code">long</code> and pointers.
</p>
</dd>
<dt><code class="code">llp64</code></dt>
<dd><p>Target has 32-bit <code class="code">int</code> and <code class="code">long</code>, 64-bit <code class="code">long long</code>
and pointers.
</p>
</dd>
<dt><code class="code">double64</code></dt>
<dd><p>Target has 64-bit <code class="code">double</code>.
</p>
</dd>
<dt><code class="code">double64plus</code></dt>
<dd><p>Target has <code class="code">double</code> that is 64 bits or longer.
</p>
</dd>
<dt><code class="code">longdouble128</code></dt>
<dd><p>Target has 128-bit <code class="code">long double</code>.
</p>
</dd>
<dt><code class="code">int32plus</code></dt>
<dd><p>Target has <code class="code">int</code> that is at 32 bits or longer.
</p>
</dd>
<dt><code class="code">int16</code></dt>
<dd><p>Target has <code class="code">int</code> that is 16 bits or shorter.
</p>
</dd>
<dt><code class="code">longlong64</code></dt>
<dd><p>Target has 64-bit <code class="code">long long</code>.
</p>
</dd>
<dt><code class="code">long_neq_int</code></dt>
<dd><p>Target has <code class="code">int</code> and <code class="code">long</code> with different sizes.
</p>
</dd>
<dt><code class="code">short_eq_int</code></dt>
<dd><p>Target has <code class="code">short</code> and <code class="code">int</code> with the same size.
</p>
</dd>
<dt><code class="code">ptr_eq_short</code></dt>
<dd><p>Target has pointers (<code class="code">void *</code>) and <code class="code">short</code> with the same size.
</p>
</dd>
<dt><code class="code">int_eq_float</code></dt>
<dd><p>Target has <code class="code">int</code> and <code class="code">float</code> with the same size.
</p>
</dd>
<dt><code class="code">ptr_eq_long</code></dt>
<dd><p>Target has pointers (<code class="code">void *</code>) and <code class="code">long</code> with the same size.
</p>
</dd>
<dt><code class="code">large_double</code></dt>
<dd><p>Target supports <code class="code">double</code> that is longer than <code class="code">float</code>.
</p>
</dd>
<dt><code class="code">large_long_double</code></dt>
<dd><p>Target supports <code class="code">long double</code> that is longer than <code class="code">double</code>.
</p>
</dd>
<dt><code class="code">ptr32plus</code></dt>
<dd><p>Target has pointers that are 32 bits or longer.
</p>
</dd>
<dt><code class="code">size20plus</code></dt>
<dd><p>Target has a 20-bit or larger address space, so supports at least
16-bit array and structure sizes.
</p>
</dd>
<dt><code class="code">size24plus</code></dt>
<dd><p>Target has a 24-bit or larger address space, so supports at least
20-bit array and structure sizes.
</p>
</dd>
<dt><code class="code">size32plus</code></dt>
<dd><p>Target has a 32-bit or larger address space, so supports at least
24-bit array and structure sizes.
</p>
</dd>
<dt><code class="code">4byte_wchar_t</code></dt>
<dd><p>Target has <code class="code">wchar_t</code> that is at least 4 bytes.
</p>
</dd>
<dt><code class="code">float<var class="var">n</var></code></dt>
<dd><p>Target has the <code class="code">_Float<var class="var">n</var></code> type.
</p>
</dd>
<dt><code class="code">float<var class="var">n</var>x</code></dt>
<dd><p>Target has the <code class="code">_Float<var class="var">n</var>x</code> type.
</p>
</dd>
<dt><code class="code">float<var class="var">n</var>_runtime</code></dt>
<dd><p>Target has the <code class="code">_Float<var class="var">n</var></code> type, including runtime support
for any options added with <code class="code">dg-add-options</code>.
</p>
</dd>
<dt><code class="code">float<var class="var">n</var>x_runtime</code></dt>
<dd><p>Target has the <code class="code">_Float<var class="var">n</var>x</code> type, including runtime support
for any options added with <code class="code">dg-add-options</code>.
</p>
</dd>
<dt><code class="code">floatn_nx_runtime</code></dt>
<dd><p>Target has runtime support for any options added with
<code class="code">dg-add-options</code> for any <code class="code">_Float<var class="var">n</var></code> or
<code class="code">_Float<var class="var">n</var>x</code> type.
</p>
</dd>
<dt><code class="code">inf</code></dt>
<dd><p>Target supports floating point infinite (<code class="code">inf</code>) for type
<code class="code">double</code>.
</p>
</dd>
<dt><code class="code">inff</code></dt>
<dd><p>Target supports floating point infinite (<code class="code">inf</code>) for type
<code class="code">float</code>.
</p></dd>
</dl>
</div>
<div class="subsubsection-level-extent" id="Fortran_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.3 Fortran-specific attributes<a class="copiable-link" href="#Fortran_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">fortran_integer_16</code></dt>
<dd><p>Target supports Fortran <code class="code">integer</code> that is 16 bytes or longer.
</p>
</dd>
<dt><code class="code">fortran_real_10</code></dt>
<dd><p>Target supports Fortran <code class="code">real</code> that is 10 bytes or longer.
</p>
</dd>
<dt><code class="code">fortran_real_16</code></dt>
<dd><p>Target supports Fortran <code class="code">real</code> that is 16 bytes or longer.
</p>
</dd>
<dt><code class="code">fortran_large_int</code></dt>
<dd><p>Target supports Fortran <code class="code">integer</code> kinds larger than <code class="code">integer(8)</code>.
</p>
</dd>
<dt><code class="code">fortran_large_real</code></dt>
<dd><p>Target supports Fortran <code class="code">real</code> kinds larger than <code class="code">real(8)</code>.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Vector_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.4 Vector-specific attributes<a class="copiable-link" href="#Vector_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">vect_align_stack_vars</code></dt>
<dd><p>The target&rsquo;s ABI allows stack variables to be aligned to the preferred
vector alignment.
</p>
</dd>
<dt><code class="code">vect_avg_qi</code></dt>
<dd><p>Target supports both signed and unsigned averaging operations on vectors
of bytes.
</p>
</dd>
<dt><code class="code">vect_mulhrs_hi</code></dt>
<dd><p>Target supports both signed and unsigned multiply-high-with-round-and-scale
operations on vectors of half-words.
</p>
</dd>
<dt><code class="code">vect_sdiv_pow2_si</code></dt>
<dd><p>Target supports signed division by constant power-of-2 operations
on vectors of 4-byte integers.
</p>
</dd>
<dt><code class="code">vect_condition</code></dt>
<dd><p>Target supports vector conditional operations.
</p>
</dd>
<dt><code class="code">vect_cond_mixed</code></dt>
<dd><p>Target supports vector conditional operations where comparison operands
have different type from the value operands.
</p>
</dd>
<dt><code class="code">vect_double</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">double</code>.
</p>
</dd>
<dt><code class="code">vect_double_cond_arith</code></dt>
<dd><p>Target supports conditional addition, subtraction, multiplication,
division, minimum and maximum on vectors of <code class="code">double</code>, via the
<code class="code">cond_</code> optabs.
</p>
</dd>
<dt><code class="code">vect_element_align_preferred</code></dt>
<dd><p>The target&rsquo;s preferred vector alignment is the same as the element
alignment.
</p>
</dd>
<dt><code class="code">vect_float</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">float</code> when
<samp class="option">-funsafe-math-optimizations</samp> is in effect.
</p>
</dd>
<dt><code class="code">vect_float_strict</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">float</code> when
<samp class="option">-funsafe-math-optimizations</samp> is not in effect.
This implies <code class="code">vect_float</code>.
</p>
</dd>
<dt><code class="code">vect_int</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_long</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">long</code>.
</p>
</dd>
<dt><code class="code">vect_long_long</code></dt>
<dd><p>Target supports hardware vectors of <code class="code">long long</code>.
</p>
</dd>
<dt><code class="code">vect_check_ptrs</code></dt>
<dd><p>Target supports the <code class="code">check_raw_ptrs</code> and <code class="code">check_war_ptrs</code>
optabs on vectors.
</p>
</dd>
<dt><code class="code">vect_fully_masked</code></dt>
<dd><p>Target supports fully-masked (also known as fully-predicated) loops,
so that vector loops can handle partial as well as full vectors.
</p>
</dd>
<dt><code class="code">vect_masked_load</code></dt>
<dd><p>Target supports vector masked loads.
</p>
</dd>
<dt><code class="code">vect_masked_store</code></dt>
<dd><p>Target supports vector masked stores.
</p>
</dd>
<dt><code class="code">vect_gather_load_ifn</code></dt>
<dd><p>Target supports vector gather loads using internal functions
(rather than via built-in functions or emulation).
</p>
</dd>
<dt><code class="code">vect_scatter_store</code></dt>
<dd><p>Target supports vector scatter stores.
</p>
</dd>
<dt><code class="code">vect_aligned_arrays</code></dt>
<dd><p>Target aligns arrays to vector alignment boundary.
</p>
</dd>
<dt><code class="code">vect_hw_misalign</code></dt>
<dd><p>Target supports a vector misalign access.
</p>
</dd>
<dt><code class="code">vect_no_align</code></dt>
<dd><p>Target does not support a vector alignment mechanism.
</p>
</dd>
<dt><code class="code">vect_peeling_profitable</code></dt>
<dd><p>Target might require to peel loops for alignment purposes.
</p>
</dd>
<dt><code class="code">vect_no_int_min_max</code></dt>
<dd><p>Target does not support a vector min and max instruction on <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_no_int_add</code></dt>
<dd><p>Target does not support a vector add instruction on <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_no_bitwise</code></dt>
<dd><p>Target does not support vector bitwise instructions.
</p>
</dd>
<dt><code class="code">vect_bool_cmp</code></dt>
<dd><p>Target supports comparison of <code class="code">bool</code> vectors for at least one
vector length.
</p>
</dd>
<dt><code class="code">vect_char_add</code></dt>
<dd><p>Target supports addition of <code class="code">char</code> vectors for at least one
vector length.
</p>
</dd>
<dt><code class="code">vect_char_mult</code></dt>
<dd><p>Target supports <code class="code">vector char</code> multiplication.
</p>
</dd>
<dt><code class="code">vect_short_mult</code></dt>
<dd><p>Target supports <code class="code">vector short</code> multiplication.
</p>
</dd>
<dt><code class="code">vect_int_mult</code></dt>
<dd><p>Target supports <code class="code">vector int</code> multiplication.
</p>
</dd>
<dt><code class="code">vect_long_mult</code></dt>
<dd><p>Target supports 64 bit <code class="code">vector long</code> multiplication.
</p>
</dd>
<dt><code class="code">vect_extract_even_odd</code></dt>
<dd><p>Target supports vector even/odd element extraction.
</p>
</dd>
<dt><code class="code">vect_extract_even_odd_wide</code></dt>
<dd><p>Target supports vector even/odd element extraction of vectors with elements
<code class="code">SImode</code> or larger.
</p>
</dd>
<dt><code class="code">vect_interleave</code></dt>
<dd><p>Target supports vector interleaving.
</p>
</dd>
<dt><code class="code">vect_strided</code></dt>
<dd><p>Target supports vector interleaving and extract even/odd.
</p>
</dd>
<dt><code class="code">vect_strided_wide</code></dt>
<dd><p>Target supports vector interleaving and extract even/odd for wide
element types.
</p>
</dd>
<dt><code class="code">vect_perm</code></dt>
<dd><p>Target supports vector permutation.
</p>
</dd>
<dt><code class="code">vect_perm_byte</code></dt>
<dd><p>Target supports permutation of vectors with 8-bit elements.
</p>
</dd>
<dt><code class="code">vect_perm_short</code></dt>
<dd><p>Target supports permutation of vectors with 16-bit elements.
</p>
</dd>
<dt><code class="code">vect_perm3_byte</code></dt>
<dd><p>Target supports permutation of vectors with 8-bit elements, and for the
default vector length it is possible to permute:
</p><div class="example">
<pre class="example-preformatted">{ a0, a1, a2, b0, b1, b2, ... }
</pre></div>
<p>to:
</p><div class="example">
<pre class="example-preformatted">{ a0, a0, a0, b0, b0, b0, ... }
{ a1, a1, a1, b1, b1, b1, ... }
{ a2, a2, a2, b2, b2, b2, ... }
</pre></div>
<p>using only two-vector permutes, regardless of how long the sequence is.
</p>
</dd>
<dt><code class="code">vect_perm3_int</code></dt>
<dd><p>Like <code class="code">vect_perm3_byte</code>, but for 32-bit elements.
</p>
</dd>
<dt><code class="code">vect_perm3_short</code></dt>
<dd><p>Like <code class="code">vect_perm3_byte</code>, but for 16-bit elements.
</p>
</dd>
<dt><code class="code">vect_shift</code></dt>
<dd><p>Target supports a hardware vector shift operation.
</p>
</dd>
<dt><code class="code">vect_unaligned_possible</code></dt>
<dd><p>Target prefers vectors to have an alignment greater than element
alignment, but also allows unaligned vector accesses in some
circumstances.
</p>
</dd>
<dt><code class="code">vect_variable_length</code></dt>
<dd><p>Target has variable-length vectors.
</p>
</dd>
<dt><code class="code">vect64</code></dt>
<dd><p>Target supports vectors of 64 bits.
</p>
</dd>
<dt><code class="code">vect32</code></dt>
<dd><p>Target supports vectors of 32 bits.
</p>
</dd>
<dt><code class="code">vect_widen_sum_hi_to_si</code></dt>
<dd><p>Target supports a vector widening summation of <code class="code">short</code> operands
into <code class="code">int</code> results, or can promote (unpack) from <code class="code">short</code>
to <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_widen_sum_qi_to_hi</code></dt>
<dd><p>Target supports a vector widening summation of <code class="code">char</code> operands
into <code class="code">short</code> results, or can promote (unpack) from <code class="code">char</code>
to <code class="code">short</code>.
</p>
</dd>
<dt><code class="code">vect_widen_sum_qi_to_si</code></dt>
<dd><p>Target supports a vector widening summation of <code class="code">char</code> operands
into <code class="code">int</code> results.
</p>
</dd>
<dt><code class="code">vect_widen_mult_qi_to_hi</code></dt>
<dd><p>Target supports a vector widening multiplication of <code class="code">char</code> operands
into <code class="code">short</code> results, or can promote (unpack) from <code class="code">char</code> to
<code class="code">short</code> and perform non-widening multiplication of <code class="code">short</code>.
</p>
</dd>
<dt><code class="code">vect_widen_mult_hi_to_si</code></dt>
<dd><p>Target supports a vector widening multiplication of <code class="code">short</code> operands
into <code class="code">int</code> results, or can promote (unpack) from <code class="code">short</code> to
<code class="code">int</code> and perform non-widening multiplication of <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_widen_mult_si_to_di_pattern</code></dt>
<dd><p>Target supports a vector widening multiplication of <code class="code">int</code> operands
into <code class="code">long</code> results.
</p>
</dd>
<dt><code class="code">vect_sdot_qi</code></dt>
<dd><p>Target supports a vector dot-product of <code class="code">signed char</code>.
</p>
</dd>
<dt><code class="code">vect_udot_qi</code></dt>
<dd><p>Target supports a vector dot-product of <code class="code">unsigned char</code>.
</p>
</dd>
<dt><code class="code">vect_usdot_qi</code></dt>
<dd><p>Target supports a vector dot-product where one operand of the multiply is
<code class="code">signed char</code> and the other of <code class="code">unsigned char</code>.
</p>
</dd>
<dt><code class="code">vect_sdot_hi</code></dt>
<dd><p>Target supports a vector dot-product of <code class="code">signed short</code>.
</p>
</dd>
<dt><code class="code">vect_udot_hi</code></dt>
<dd><p>Target supports a vector dot-product of <code class="code">unsigned short</code>.
</p>
</dd>
<dt><code class="code">vect_pack_trunc</code></dt>
<dd><p>Target supports a vector demotion (packing) of <code class="code">short</code> to <code class="code">char</code>
and from <code class="code">int</code> to <code class="code">short</code> using modulo arithmetic.
</p>
</dd>
<dt><code class="code">vect_unpack</code></dt>
<dd><p>Target supports a vector promotion (unpacking) of <code class="code">char</code> to <code class="code">short</code>
and from <code class="code">char</code> to <code class="code">int</code>.
</p>
</dd>
<dt><code class="code">vect_intfloat_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">signed int</code> to <code class="code">float</code>.
</p>
</dd>
<dt><code class="code">vect_uintfloat_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">unsigned int</code> to <code class="code">float</code>.
</p>
</dd>
<dt><code class="code">vect_floatint_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">float</code> to <code class="code">signed int</code>.
</p>
</dd>
<dt><code class="code">vect_floatuint_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">float</code> to <code class="code">unsigned int</code>.
</p>
</dd>
<dt><code class="code">vect_intdouble_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">signed int</code> to <code class="code">double</code>.
</p>
</dd>
<dt><code class="code">vect_doubleint_cvt</code></dt>
<dd><p>Target supports conversion from <code class="code">double</code> to <code class="code">signed int</code>.
</p>
</dd>
<dt><code class="code">vect_max_reduc</code></dt>
<dd><p>Target supports max reduction for vectors.
</p>
</dd>
<dt><code class="code">vect_sizes_16B_8B</code></dt>
<dd><p>Target supports 16- and 8-bytes vectors.
</p>
</dd>
<dt><code class="code">vect_sizes_32B_16B</code></dt>
<dd><p>Target supports 32- and 16-bytes vectors.
</p>
</dd>
<dt><code class="code">vect_logical_reduc</code></dt>
<dd><p>Target supports AND, IOR and XOR reduction on vectors.
</p>
</dd>
<dt><code class="code">vect_fold_extract_last</code></dt>
<dd><p>Target supports the <code class="code">fold_extract_last</code> optab.
</p>
</dd>
<dt><code class="code">vect_len_load_store</code></dt>
<dd><p>Target supports the <code class="code">len_load</code> and <code class="code">len_store</code> optabs.
</p>
</dd>
<dt><code class="code">vect_partial_vectors_usage_1</code></dt>
<dd><p>Target supports loop vectorization with partial vectors and
<code class="code">vect-partial-vector-usage</code> is set to 1.
</p>
</dd>
<dt><code class="code">vect_partial_vectors_usage_2</code></dt>
<dd><p>Target supports loop vectorization with partial vectors and
<code class="code">vect-partial-vector-usage</code> is set to 2.
</p>
</dd>
<dt><code class="code">vect_partial_vectors</code></dt>
<dd><p>Target supports loop vectorization with partial vectors and
<code class="code">vect-partial-vector-usage</code> is nonzero.
</p>
</dd>
<dt><code class="code">vect_slp_v2qi_store_align</code></dt>
<dd><p>Target supports vectorization of 2-byte char stores with 2-byte aligned
address at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v4qi_store_align</code></dt>
<dd><p>Target supports vectorization of 4-byte char stores with 4-byte aligned
address at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v4qi_store_unalign</code></dt>
<dd><p>Target supports vectorization of 4-byte char stores with unaligned address
at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">struct_4char_block_move</code></dt>
<dd><p>Target supports block move for 8-byte aligned 4-byte size struct initialization.
</p>
</dd>
<dt><code class="code">vect_slp_v4qi_store_unalign_1</code></dt>
<dd><p>Target supports vectorization of 4-byte char stores with unaligned address
or store them with constant pool at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">struct_8char_block_move</code></dt>
<dd><p>Target supports block move for 8-byte aligned 8-byte size struct initialization.
</p>
</dd>
<dt><code class="code">vect_slp_v8qi_store_unalign_1</code></dt>
<dd><p>Target supports vectorization of 8-byte char stores with unaligned address
or store them with constant pool at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">struct_16char_block_move</code></dt>
<dd><p>Target supports block move for 8-byte aligned 16-byte size struct
initialization.
</p>
</dd>
<dt><code class="code">vect_slp_v16qi_store_unalign_1</code></dt>
<dd><p>Target supports vectorization of 16-byte char stores with unaligned address
or store them with constant pool at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v2hi_store_align</code></dt>
<dd><p>Target supports vectorization of 4-byte short stores with 4-byte aligned
addressat plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v2hi_store_unalign</code></dt>
<dd><p>Target supports vectorization of 4-byte short stores with unaligned address
at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v4hi_store_unalign</code></dt>
<dd><p>Target supports vectorization of 8-byte short stores with unaligned address
at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v2si_store_align</code></dt>
<dd><p>Target supports vectorization of 8-byte int stores with 8-byte aligned address
at plain <samp class="option">-O2</samp>.
</p>
</dd>
<dt><code class="code">vect_slp_v4si_store_unalign</code></dt>
<dd><p>Target supports vectorization of 16-byte int stores with unaligned address
at plain <samp class="option">-O2</samp>.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Thread-Local-Storage-attributes">
<h4 class="subsubsection"><span>7.2.3.5 Thread Local Storage attributes<a class="copiable-link" href="#Thread-Local-Storage-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">tls</code></dt>
<dd><p>Target supports thread-local storage.
</p>
</dd>
<dt><code class="code">tls_native</code></dt>
<dd><p>Target supports native (rather than emulated) thread-local storage.
</p>
</dd>
<dt><code class="code">tls_runtime</code></dt>
<dd><p>Test system supports executing TLS executables.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Decimal-floating-point-attributes">
<h4 class="subsubsection"><span>7.2.3.6 Decimal floating point attributes<a class="copiable-link" href="#Decimal-floating-point-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">dfp</code></dt>
<dd><p>Targets supports compiling decimal floating point extension to C.
</p>
</dd>
<dt><code class="code">dfp_nocache</code></dt>
<dd><p>Including the options used to compile this particular test, the
target supports compiling decimal floating point extension to C.
</p>
</dd>
<dt><code class="code">dfprt</code></dt>
<dd><p>Test system can execute decimal floating point tests.
</p>
</dd>
<dt><code class="code">dfprt_nocache</code></dt>
<dd><p>Including the options used to compile this particular test, the
test system can execute decimal floating point tests.
</p>
</dd>
<dt><code class="code">hard_dfp</code></dt>
<dd><p>Target generates decimal floating point instructions with current options.
</p>
</dd>
<dt><code class="code">dfp_bid</code></dt>
<dd><p>Target uses the BID format for decimal floating point.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="ARM_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.7 ARM-specific attributes<a class="copiable-link" href="#ARM_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">arm32</code></dt>
<dd><p>ARM target generates 32-bit code.
</p>
</dd>
<dt><code class="code">arm_little_endian</code></dt>
<dd><p>ARM target that generates little-endian code.
</p>
</dd>
<dt><code class="code">arm_eabi</code></dt>
<dd><p>ARM target adheres to the ABI for the ARM Architecture.
</p>
</dd>
<dt><code class="code">arm_fp_ok</code></dt>
<dd><a class="anchor" id="arm_005ffp_005fok"></a><p>ARM target defines <code class="code">__ARM_FP</code> using <code class="code">-mfloat-abi=softfp</code> or
equivalent options.  Some multilibs may be incompatible with these
options.
</p>
</dd>
<dt><code class="code">arm_fp_dp_ok</code></dt>
<dd><a class="anchor" id="arm_005ffp_005fdp_005fok"></a><p>ARM target defines <code class="code">__ARM_FP</code> with double-precision support using
<code class="code">-mfloat-abi=softfp</code> or equivalent options.  Some multilibs may
be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_hf_eabi</code></dt>
<dd><p>ARM target adheres to the VFP and Advanced SIMD Register Arguments
variant of the ABI for the ARM Architecture (as selected with
<code class="code">-mfloat-abi=hard</code>).
</p>
</dd>
<dt><code class="code">arm_softfloat</code></dt>
<dd><p>ARM target uses emulated floating point operations.
</p>
</dd>
<dt><code class="code">arm_hard_vfp_ok</code></dt>
<dd><p>ARM target supports <code class="code">-mfpu=vfp -mfloat-abi=hard</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_iwmmxt_ok</code></dt>
<dd><p>ARM target supports <code class="code">-mcpu=iwmmxt</code>.
Some multilibs may be incompatible with this option.
</p>
</dd>
<dt><code class="code">arm_neon</code></dt>
<dd><p>ARM target supports generating NEON instructions.
</p>
</dd>
<dt><code class="code">arm_tune_string_ops_prefer_neon</code></dt>
<dd><p>Test CPU tune supports inlining string operations with NEON instructions.
</p>
</dd>
<dt><code class="code">arm_neon_hw</code></dt>
<dd><p>Test system supports executing NEON instructions.
</p>
</dd>
<dt><code class="code">arm_neonv2_hw</code></dt>
<dd><p>Test system supports executing NEON v2 instructions.
</p>
</dd>
<dt><code class="code">arm_neon_ok</code></dt>
<dd><a class="anchor" id="arm_005fneon_005fok"></a><p>ARM Target supports <code class="code">-mfpu=neon -mfloat-abi=softfp</code> or compatible
options.  Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_neon_ok_no_float_abi</code></dt>
<dd><a class="anchor" id="arm_005fneon_005fok_005fno_005ffloat_005fabi"></a><p>ARM Target supports NEON with <code class="code">-mfpu=neon</code>, but without any
-mfloat-abi= option.  Some multilibs may be incompatible with this
option.
</p>
</dd>
<dt><code class="code">arm_neonv2_ok</code></dt>
<dd><a class="anchor" id="arm_005fneonv2_005fok"></a><p>ARM Target supports <code class="code">-mfpu=neon-vfpv4 -mfloat-abi=softfp</code> or compatible
options.  Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_fp16_ok</code></dt>
<dd><a class="anchor" id="arm_005ffp16_005fok"></a><p>Target supports options to generate VFP half-precision floating-point
instructions.  Some multilibs may be incompatible with these
options.  This test is valid for ARM only.
</p>
</dd>
<dt><code class="code">arm_fp16_hw</code></dt>
<dd><p>Target supports executing VFP half-precision floating-point
instructions.  This test is valid for ARM only.
</p>
</dd>
<dt><code class="code">arm_neon_fp16_ok</code></dt>
<dd><a class="anchor" id="arm_005fneon_005ffp16_005fok"></a><p>ARM Target supports <code class="code">-mfpu=neon-fp16 -mfloat-abi=softfp</code> or compatible
options, including <code class="code">-mfp16-format=ieee</code> if necessary to obtain the
<code class="code">__fp16</code> type.  Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_neon_fp16_hw</code></dt>
<dd><p>Test system supports executing Neon half-precision float instructions.
(Implies previous.)
</p>
</dd>
<dt><code class="code">arm_fp16_alternative_ok</code></dt>
<dd><p>ARM target supports the ARM FP16 alternative format.  Some multilibs
may be incompatible with the options needed.
</p>
</dd>
<dt><code class="code">arm_fp16_none_ok</code></dt>
<dd><p>ARM target supports specifying none as the ARM FP16 format.
</p>
</dd>
<dt><code class="code">arm_thumb1_ok</code></dt>
<dd><p>ARM target generates Thumb-1 code for <code class="code">-mthumb</code>.
</p>
</dd>
<dt><code class="code">arm_thumb2_ok</code></dt>
<dd><p>ARM target generates Thumb-2 code for <code class="code">-mthumb</code>.
</p>
</dd>
<dt><code class="code">arm_nothumb</code></dt>
<dd><p>ARM target that is not using Thumb.
</p>
</dd>
<dt><code class="code">arm_vfp_ok</code></dt>
<dd><p>ARM target supports <code class="code">-mfpu=vfp -mfloat-abi=softfp</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_vfp3_ok</code></dt>
<dd><a class="anchor" id="arm_005fvfp3_005fok"></a><p>ARM target supports <code class="code">-mfpu=vfp3 -mfloat-abi=softfp</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_arch_v8a_hard_ok</code></dt>
<dd><a class="anchor" id="arm_005farch_005fv8a_005fhard_005fok"></a><p>The compiler is targeting <code class="code">arm*-*-*</code> and can compile and assemble code
using the options <code class="code">-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard</code>.
This is not enough to guarantee that linking works.
</p>
</dd>
<dt><code class="code">arm_arch_v8a_hard_multilib</code></dt>
<dd><p>The compiler is targeting <code class="code">arm*-*-*</code> and can build programs using
the options <code class="code">-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard</code>.
The target can also run the resulting binaries.
</p>
</dd>
<dt><code class="code">arm_v8_vfp_ok</code></dt>
<dd><p>ARM target supports <code class="code">-mfpu=fp-armv8 -mfloat-abi=softfp</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_neon_ok</code></dt>
<dd><p>ARM target supports <code class="code">-mfpu=neon-fp-armv8 -mfloat-abi=softfp</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_1a_neon_ok</code></dt>
<dd><a class="anchor" id="arm_005fv8_005f1a_005fneon_005fok"></a><p>ARM target supports options to generate ARMv8.1-A Adv.SIMD instructions.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_1a_neon_hw</code></dt>
<dd><p>ARM target supports executing ARMv8.1-A Adv.SIMD instructions.  Some
multilibs may be incompatible with the options needed.  Implies
arm_v8_1a_neon_ok.
</p>
</dd>
<dt><code class="code">arm_acq_rel</code></dt>
<dd><p>ARM target supports acquire-release instructions.
</p>
</dd>
<dt><code class="code">arm_v8_2a_fp16_scalar_ok</code></dt>
<dd><a class="anchor" id="arm_005fv8_005f2a_005ffp16_005fscalar_005fok"></a><p>ARM target supports options to generate instructions for ARMv8.2-A and
scalar instructions from the FP16 extension.  Some multilibs may be
incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_2a_fp16_scalar_hw</code></dt>
<dd><p>ARM target supports executing instructions for ARMv8.2-A and scalar
instructions from the FP16 extension.  Some multilibs may be
incompatible with these options.  Implies arm_v8_2a_fp16_neon_ok.
</p>
</dd>
<dt><code class="code">arm_v8_2a_fp16_neon_ok</code></dt>
<dd><a class="anchor" id="arm_005fv8_005f2a_005ffp16_005fneon_005fok"></a><p>ARM target supports options to generate instructions from ARMv8.2-A with
the FP16 extension.  Some multilibs may be incompatible with these
options.  Implies arm_v8_2a_fp16_scalar_ok.
</p>
</dd>
<dt><code class="code">arm_v8_2a_fp16_neon_hw</code></dt>
<dd><p>ARM target supports executing instructions from ARMv8.2-A with the FP16
extension.  Some multilibs may be incompatible with these options.
Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.
</p>
</dd>
<dt><code class="code">arm_v8_2a_dotprod_neon_ok</code></dt>
<dd><a class="anchor" id="arm_005fv8_005f2a_005fdotprod_005fneon_005fok"></a><p>ARM target supports options to generate instructions from ARMv8.2-A with
the Dot Product extension. Some multilibs may be incompatible with these
options.
</p>
</dd>
<dt><code class="code">arm_v8_2a_dotprod_neon_hw</code></dt>
<dd><p>ARM target supports executing instructions from ARMv8.2-A with the Dot
Product extension. Some multilibs may be incompatible with these options.
Implies arm_v8_2a_dotprod_neon_ok.
</p>
</dd>
<dt><code class="code">arm_v8_2a_i8mm_neon_hw</code></dt>
<dd><p>ARM target supports executing instructions from ARMv8.2-A with the 8-bit
Matrix Multiply extension.  Some multilibs may be incompatible with these
options.  Implies arm_v8_2a_i8mm_ok.
</p>
</dd>
<dt><code class="code">arm_fp16fml_neon_ok</code></dt>
<dd><a class="anchor" id="arm_005ffp16fml_005fneon_005fok"></a><p>ARM target supports extensions to generate the <code class="code">VFMAL</code> and <code class="code">VFMLS</code>
half-precision floating-point instructions available from ARMv8.2-A and
onwards.  Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_2a_bf16_neon_ok</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8.2-A with
the BFloat16 extension (bf16). Some multilibs may be incompatible with these
options.
</p>
</dd>
<dt><code class="code">arm_v8_2a_i8mm_ok</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8.2-A with
the 8-Bit Integer Matrix Multiply extension (i8mm). Some multilibs may be
incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_1m_mve_ok</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8.1-M with
the M-Profile Vector Extension (MVE). Some multilibs may be incompatible
with these options.
</p>
</dd>
<dt><code class="code">arm_v8_1m_mve_fp_ok</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8.1-M with
the Half-precision floating-point instructions (HP), Floating-point Extension
(FP) along with M-Profile Vector Extension (MVE). Some multilibs may be
incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_mve_hw</code></dt>
<dd><p>Test system supports executing MVE instructions.
</p>
</dd>
<dt><code class="code">arm_v8m_main_cde</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8-M with
the Custom Datapath Extension (CDE). Some multilibs may be incompatible
with these options.
</p>
</dd>
<dt><code class="code">arm_v8m_main_cde_fp</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8-M with
the Custom Datapath Extension (CDE) and floating-point (VFP).
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_v8_1m_main_cde_mve</code></dt>
<dd><p>ARM target supports options to generate instructions from ARMv8.1-M with
the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE).
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_pacbti_hw</code></dt>
<dd><p>Test system supports executing Pointer Authentication and Branch Target
Identification instructions.
</p>
</dd>
<dt><code class="code">arm_prefer_ldrd_strd</code></dt>
<dd><p>ARM target prefers <code class="code">LDRD</code> and <code class="code">STRD</code> instructions over
<code class="code">LDM</code> and <code class="code">STM</code> instructions.
</p>
</dd>
<dt><code class="code">arm_thumb1_movt_ok</code></dt>
<dd><p>ARM target generates Thumb-1 code for <code class="code">-mthumb</code> with <code class="code">MOVW</code>
and <code class="code">MOVT</code> instructions available.
</p>
</dd>
<dt><code class="code">arm_thumb1_cbz_ok</code></dt>
<dd><p>ARM target generates Thumb-1 code for <code class="code">-mthumb</code> with
<code class="code">CBZ</code> and <code class="code">CBNZ</code> instructions available.
</p>
</dd>
<dt><code class="code">arm_divmod_simode</code></dt>
<dd><p>ARM target for which divmod transform is disabled, if it supports hardware
div instruction.
</p>
</dd>
<dt><code class="code">arm_cmse_ok</code></dt>
<dd><p>ARM target supports ARMv8-M Security Extensions, enabled by the <code class="code">-mcmse</code>
option.
</p>
</dd>
<dt><code class="code">arm_cmse_hw</code></dt>
<dd><p>Test system supports executing CMSE instructions.
</p>
</dd>
<dt><code class="code">arm_coproc1_ok</code></dt>
<dd><a class="anchor" id="arm_005fcoproc1_005fok"></a><p>ARM target supports the following coprocessor instructions: <code class="code">CDP</code>,
<code class="code">LDC</code>, <code class="code">STC</code>, <code class="code">MCR</code> and <code class="code">MRC</code>.
</p>
</dd>
<dt><code class="code">arm_coproc2_ok</code></dt>
<dd><a class="anchor" id="arm_005fcoproc2_005fok"></a><p>ARM target supports all the coprocessor instructions also listed as supported
in <a class="ref" href="#arm_005fcoproc1_005fok">arm_coproc1_ok</a> in addition to the following: <code class="code">CDP2</code>, <code class="code">LDC2</code>,
<code class="code">LDC2l</code>, <code class="code">STC2</code>, <code class="code">STC2l</code>, <code class="code">MCR2</code> and <code class="code">MRC2</code>.
</p>
</dd>
<dt><code class="code">arm_coproc3_ok</code></dt>
<dd><a class="anchor" id="arm_005fcoproc3_005fok"></a><p>ARM target supports all the coprocessor instructions also listed as supported
in <a class="ref" href="#arm_005fcoproc2_005fok">arm_coproc2_ok</a> in addition the following: <code class="code">MCRR</code> and <code class="code">MRRC</code>.
</p>
</dd>
<dt><code class="code">arm_coproc4_ok</code></dt>
<dd><p>ARM target supports all the coprocessor instructions also listed as supported
in <a class="ref" href="#arm_005fcoproc3_005fok">arm_coproc3_ok</a> in addition the following: <code class="code">MCRR2</code> and <code class="code">MRRC2</code>.
</p>
</dd>
<dt><code class="code">arm_simd32_ok</code></dt>
<dd><a class="anchor" id="arm_005fsimd32_005fok"></a><p>ARM Target supports options suitable for accessing the SIMD32 intrinsics from
<code class="code">arm_acle.h</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_sat_ok</code></dt>
<dd><a class="anchor" id="arm_005fsat_005fok"></a><p>ARM Target supports options suitable for accessing the saturation
intrinsics from <code class="code">arm_acle.h</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_dsp_ok</code></dt>
<dd><a class="anchor" id="arm_005fdsp_005fok"></a><p>ARM Target supports options suitable for accessing the DSP intrinsics
from <code class="code">arm_acle.h</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_softfp_ok</code></dt>
<dd><a class="anchor" id="arm_005fsoftfp_005fok"></a><p>ARM target supports the <code class="code">-mfloat-abi=softfp</code> option.
</p>
</dd>
<dt><code class="code">arm_hard_ok</code></dt>
<dd><a class="anchor" id="arm_005fhard_005fok"></a><p>ARM target supports the <code class="code">-mfloat-abi=hard</code> option.
</p>
</dd>
<dt><code class="code">arm_mve</code></dt>
<dd><a class="anchor" id="arm_005fmve"></a><p>ARM target supports generating MVE instructions.
</p>
</dd>
<dt><code class="code">arm_v8_1_lob_ok</code></dt>
<dd><a class="anchor" id="arm_005fv8_005f1_005flob_005fok"></a><p>ARM Target supports executing the Armv8.1-M Mainline Low Overhead Loop
instructions <code class="code">DLS</code> and <code class="code">LE</code>.
Some multilibs may be incompatible with these options.
</p>
</dd>
<dt><code class="code">arm_thumb2_no_arm_v8_1_lob</code></dt>
<dd><p>ARM target where Thumb-2 is used without options but does not support
executing the Armv8.1-M Mainline Low Overhead Loop instructions
<code class="code">DLS</code> and <code class="code">LE</code>.
</p>
</dd>
<dt><code class="code">arm_thumb2_ok_no_arm_v8_1_lob</code></dt>
<dd><p>ARM target generates Thumb-2 code for <code class="code">-mthumb</code> but does not
support executing the Armv8.1-M Mainline Low Overhead Loop
instructions <code class="code">DLS</code> and <code class="code">LE</code>.
</p>
</dd>
<dt><code class="code">mbranch_protection_ok</code></dt>
<dd><p>ARM target supporting <code class="code">-mbranch-protection=standard</code>.
</p>
</dd>
<dt><code class="code">arm_pacbti_hw</code></dt>
<dd><p>Test system supports for executing non nop pacbti instructions.
</p>
</dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="AArch64_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.8 AArch64-specific attributes<a class="copiable-link" href="#AArch64_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">aarch64_asm_&lt;ext&gt;_ok</code></dt>
<dd><p>AArch64 assembler supports the architecture extension <code class="code">ext</code> via the
<code class="code">.arch_extension</code> pseudo-op.
</p></dd>
<dt><code class="code">aarch64_tiny</code></dt>
<dd><p>AArch64 target which generates instruction sequences for tiny memory model.
</p></dd>
<dt><code class="code">aarch64_small</code></dt>
<dd><p>AArch64 target which generates instruction sequences for small memory model.
</p></dd>
<dt><code class="code">aarch64_large</code></dt>
<dd><p>AArch64 target which generates instruction sequences for large memory model.
</p></dd>
<dt><code class="code">aarch64_little_endian</code></dt>
<dd><p>AArch64 target which generates instruction sequences for little endian.
</p></dd>
<dt><code class="code">aarch64_big_endian</code></dt>
<dd><p>AArch64 target which generates instruction sequences for big endian.
</p></dd>
<dt><code class="code">aarch64_small_fpic</code></dt>
<dd><p>Binutils installed on test system supports relocation types required by -fpic
for AArch64 small memory model.
</p></dd>
<dt><code class="code">aarch64_sve_hw</code></dt>
<dd><p>AArch64 target that is able to generate and execute SVE code (regardless of
whether it does so by default).
</p></dd>
<dt><code class="code">aarch64_sve128_hw</code></dt>
<dt><code class="code">aarch64_sve256_hw</code></dt>
<dt><code class="code">aarch64_sve512_hw</code></dt>
<dt><code class="code">aarch64_sve1024_hw</code></dt>
<dt><code class="code">aarch64_sve2048_hw</code></dt>
<dd><p>Like <code class="code">aarch64_sve_hw</code>, but also test for an exact hardware vector length.
</p>
</dd>
<dt><code class="code">aarch64_fjcvtzs_hw</code></dt>
<dd><p>AArch64 target that is able to generate and execute armv8.3-a FJCVTZS
instruction.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="MIPS_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.9 MIPS-specific attributes<a class="copiable-link" href="#MIPS_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">mips64</code></dt>
<dd><p>MIPS target supports 64-bit instructions.
</p>
</dd>
<dt><code class="code">nomips16</code></dt>
<dd><p>MIPS target does not produce MIPS16 code.
</p>
</dd>
<dt><code class="code">mips16_attribute</code></dt>
<dd><p>MIPS target can generate MIPS16 code.
</p>
</dd>
<dt><code class="code">mips_loongson</code></dt>
<dd><p>MIPS target is a Loongson-2E or -2F target using an ABI that supports
the Loongson vector modes.
</p>
</dd>
<dt><code class="code">mips_msa</code></dt>
<dd><p>MIPS target supports <code class="code">-mmsa</code>, MIPS SIMD Architecture (MSA).
</p>
</dd>
<dt><code class="code">mips_newabi_large_long_double</code></dt>
<dd><p>MIPS target supports <code class="code">long double</code> larger than <code class="code">double</code>
when using the new ABI.
</p>
</dd>
<dt><code class="code">mpaired_single</code></dt>
<dd><p>MIPS target supports <code class="code">-mpaired-single</code>.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="MSP430_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.10 MSP430-specific attributes<a class="copiable-link" href="#MSP430_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">msp430_small</code></dt>
<dd><p>MSP430 target has the small memory model enabled (<code class="code">-msmall</code>).
</p>
</dd>
<dt><code class="code">msp430_large</code></dt>
<dd><p>MSP430 target has the large memory model enabled (<code class="code">-mlarge</code>).
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="PowerPC_002dspecific-attributes">
<h4 class="subsubsection"><span>7.2.3.11 PowerPC-specific attributes<a class="copiable-link" href="#PowerPC_002dspecific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">dfp_hw</code></dt>
<dd><p>PowerPC target supports executing hardware DFP instructions.
</p>
</dd>
<dt><code class="code">p8vector_hw</code></dt>
<dd><p>PowerPC target supports executing VSX instructions (ISA 2.07).
</p>
</dd>
<dt><code class="code">powerpc64</code></dt>
<dd><p>Test system supports executing 64-bit instructions.
</p>
</dd>
<dt><code class="code">powerpc_altivec</code></dt>
<dd><p>PowerPC target supports AltiVec.
</p>
</dd>
<dt><code class="code">powerpc_altivec_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-maltivec</code>.
</p>
</dd>
<dt><code class="code">powerpc_eabi_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-meabi</code>.
</p>
</dd>
<dt><code class="code">powerpc_elfv2</code></dt>
<dd><p>PowerPC target supports <code class="code">-mabi=elfv2</code>.
</p>
</dd>
<dt><code class="code">powerpc_fprs</code></dt>
<dd><p>PowerPC target supports floating-point registers.
</p>
</dd>
<dt><code class="code">powerpc_hard_double</code></dt>
<dd><p>PowerPC target supports hardware double-precision floating-point.
</p>
</dd>
<dt><code class="code">powerpc_htm_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-mhtm</code>
</p>
</dd>
<dt><code class="code">powerpc_p8vector_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-mpower8-vector</code>
</p>
</dd>
<dt><code class="code">powerpc_popcntb_ok</code></dt>
<dd><p>PowerPC target supports the <code class="code">popcntb</code> instruction, indicating
that this target supports <code class="code">-mcpu=power5</code>.
</p>
</dd>
<dt><code class="code">powerpc_ppu_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-mcpu=cell</code>.
</p>
</dd>
<dt><code class="code">powerpc_spe</code></dt>
<dd><p>PowerPC target supports PowerPC SPE.
</p>
</dd>
<dt><code class="code">powerpc_spe_nocache</code></dt>
<dd><p>Including the options used to compile this particular test, the
PowerPC target supports PowerPC SPE.
</p>
</dd>
<dt><code class="code">powerpc_spu</code></dt>
<dd><p>PowerPC target supports PowerPC SPU.
</p>
</dd>
<dt><code class="code">powerpc_vsx_ok</code></dt>
<dd><p>PowerPC target supports <code class="code">-mvsx</code>.
</p>
</dd>
<dt><code class="code">powerpc_405_nocache</code></dt>
<dd><p>Including the options used to compile this particular test, the
PowerPC target supports PowerPC 405.
</p>
</dd>
<dt><code class="code">ppc_recip_hw</code></dt>
<dd><p>PowerPC target supports executing reciprocal estimate instructions.
</p>
</dd>
<dt><code class="code">vmx_hw</code></dt>
<dd><p>PowerPC target supports executing AltiVec instructions.
</p>
</dd>
<dt><code class="code">vsx_hw</code></dt>
<dd><p>PowerPC target supports executing VSX instructions (ISA 2.06).
</p>
</dd>
<dt><code class="code">has_arch_pwr5</code></dt>
<dd><p>PowerPC target pre-defines macro _ARCH_PWR5 which means the <code class="code">-mcpu</code>
setting is Power5 or later.
</p>
</dd>
<dt><code class="code">has_arch_pwr6</code></dt>
<dd><p>PowerPC target pre-defines macro _ARCH_PWR6 which means the <code class="code">-mcpu</code>
setting is Power6 or later.
</p>
</dd>
<dt><code class="code">has_arch_pwr7</code></dt>
<dd><p>PowerPC target pre-defines macro _ARCH_PWR7 which means the <code class="code">-mcpu</code>
setting is Power7 or later.
</p>
</dd>
<dt><code class="code">has_arch_pwr8</code></dt>
<dd><p>PowerPC target pre-defines macro _ARCH_PWR8 which means the <code class="code">-mcpu</code>
setting is Power8 or later.
</p>
</dd>
<dt><code class="code">has_arch_pwr9</code></dt>
<dd><p>PowerPC target pre-defines macro _ARCH_PWR9 which means the <code class="code">-mcpu</code>
setting is Power9 or later.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="RISC_002dV-specific-attributes">
<h4 class="subsubsection"><span>7.2.3.12 RISC-V specific attributes<a class="copiable-link" href="#RISC_002dV-specific-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">rv32</code></dt>
<dd><p>Test system has an integer register width of 32 bits.
</p>
</dd>
<dt><code class="code">rv64</code></dt>
<dd><p>Test system has an integer register width of 64 bits.
</p>
</dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Other-hardware-attributes">
<h4 class="subsubsection"><span>7.2.3.13 Other hardware attributes<a class="copiable-link" href="#Other-hardware-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">autoincdec</code></dt>
<dd><p>Target supports autoincrement/decrement addressing.
</p>
</dd>
<dt><code class="code">avx</code></dt>
<dd><p>Target supports compiling <code class="code">avx</code> instructions.
</p>
</dd>
<dt><code class="code">avx_runtime</code></dt>
<dd><p>Target supports the execution of <code class="code">avx</code> instructions.
</p>
</dd>
<dt><code class="code">avx2</code></dt>
<dd><p>Target supports compiling <code class="code">avx2</code> instructions.
</p>
</dd>
<dt><code class="code">avx2_runtime</code></dt>
<dd><p>Target supports the execution of <code class="code">avx2</code> instructions.
</p>
</dd>
<dt><code class="code">avxvnni</code></dt>
<dd><p>Target supports the execution of <code class="code">avxvnni</code> instructions.
</p>
</dd>
<dt><code class="code">avx512f</code></dt>
<dd><p>Target supports compiling <code class="code">avx512f</code> instructions.
</p>
</dd>
<dt><code class="code">avx512f_runtime</code></dt>
<dd><p>Target supports the execution of <code class="code">avx512f</code> instructions.
</p>
</dd>
<dt><code class="code">avx512vp2intersect</code></dt>
<dd><p>Target supports the execution of <code class="code">avx512vp2intersect</code> instructions.
</p>
</dd>
<dt><code class="code">avxifma</code></dt>
<dd><p>Target supports the execution of <code class="code">avxifma</code> instructions.
</p>
</dd>
<dt><code class="code">avxneconvert</code></dt>
<dd><p>Target supports the execution of <code class="code">avxneconvert</code> instructions.
</p>
</dd>
<dt><code class="code">avxvnniint8</code></dt>
<dd><p>Target supports the execution of <code class="code">avxvnniint8</code> instructions.
</p>
</dd>
<dt><code class="code">amx_tile</code></dt>
<dd><p>Target supports the execution of <code class="code">amx-tile</code> instructions.
</p>
</dd>
<dt><code class="code">amx_int8</code></dt>
<dd><p>Target supports the execution of <code class="code">amx-int8</code> instructions.
</p>
</dd>
<dt><code class="code">amx_bf16</code></dt>
<dd><p>Target supports the execution of <code class="code">amx-bf16</code> instructions.
</p>
</dd>
<dt><code class="code">amx_complex</code></dt>
<dd><p>Target supports the execution of <code class="code">amx-complex</code> instructions.
</p>
</dd>
<dt><code class="code">amx_fp16</code></dt>
<dd><p>Target supports the execution of <code class="code">amx-fp16</code> instructions.
</p>
</dd>
<dt><code class="code">cell_hw</code></dt>
<dd><p>Test system can execute AltiVec and Cell PPU instructions.
</p>
</dd>
<dt><code class="code">clz</code></dt>
<dd><p>Target supports a clz optab on int.
</p>
</dd>
<dt><code class="code">clzl</code></dt>
<dd><p>Target supports a clz optab on long.
</p>
</dd>
<dt><code class="code">clzll</code></dt>
<dd><p>Target supports a clz optab on long long.
</p>
</dd>
<dt><code class="code">ctz</code></dt>
<dd><p>Target supports a ctz optab on int.
</p>
</dd>
<dt><code class="code">ctzl</code></dt>
<dd><p>Target supports a ctz optab on long.
</p>
</dd>
<dt><code class="code">ctzll</code></dt>
<dd><p>Target supports a ctz optab on long long.
</p>
</dd>
<dt><code class="code">cmpccxadd</code></dt>
<dd><p>Target supports the execution of <code class="code">cmpccxadd</code> instructions.
</p>
</dd>
<dt><code class="code">coldfire_fpu</code></dt>
<dd><p>Target uses a ColdFire FPU.
</p>
</dd>
<dt><code class="code">divmod</code></dt>
<dd><p>Target supporting hardware divmod insn or divmod libcall.
</p>
</dd>
<dt><code class="code">divmod_simode</code></dt>
<dd><p>Target supporting hardware divmod insn or divmod libcall for SImode.
</p>
</dd>
<dt><code class="code">hard_float</code></dt>
<dd><p>Target supports FPU instructions.
</p>
</dd>
<dt><code class="code">non_strict_align</code></dt>
<dd><p>Target does not require strict alignment.
</p>
</dd>
<dt><code class="code">pie_copyreloc</code></dt>
<dd><p>The x86-64 target linker supports PIE with copy reloc.
</p>
</dd>
<dt><code class="code">popcount</code></dt>
<dd><p>Target supports a popcount optab on int.
</p>
</dd>
<dt><code class="code">popcountl</code></dt>
<dd><p>Target supports a popcount optab on long.
</p>
</dd>
<dt><code class="code">popcountll</code></dt>
<dd><p>Target supports a popcount optab on long long.
</p>
</dd>
<dt><code class="code">prefetchi</code></dt>
<dd><p>Target supports the execution of <code class="code">prefetchi</code> instructions.
</p>
</dd>
<dt><code class="code">raoint</code></dt>
<dd><p>Target supports the execution of <code class="code">raoint</code> instructions.
</p>
</dd>
<dt><code class="code">rdrand</code></dt>
<dd><p>Target supports x86 <code class="code">rdrand</code> instruction.
</p>
</dd>
<dt><code class="code">sqrt_insn</code></dt>
<dd><p>Target has a square root instruction that the compiler can generate.
</p>
</dd>
<dt><code class="code">sse</code></dt>
<dd><p>Target supports compiling <code class="code">sse</code> instructions.
</p>
</dd>
<dt><code class="code">sse_runtime</code></dt>
<dd><p>Target supports the execution of <code class="code">sse</code> instructions.
</p>
</dd>
<dt><code class="code">sse2</code></dt>
<dd><p>Target supports compiling <code class="code">sse2</code> instructions.
</p>
</dd>
<dt><code class="code">sse2_runtime</code></dt>
<dd><p>Target supports the execution of <code class="code">sse2</code> instructions.
</p>
</dd>
<dt><code class="code">sync_char_short</code></dt>
<dd><p>Target supports atomic operations on <code class="code">char</code> and <code class="code">short</code>.
</p>
</dd>
<dt><code class="code">sync_int_long</code></dt>
<dd><p>Target supports atomic operations on <code class="code">int</code> and <code class="code">long</code>.
</p>
</dd>
<dt><code class="code">ultrasparc_hw</code></dt>
<dd><p>Test environment appears to run executables on a simulator that
accepts only <code class="code">EM_SPARC</code> executables and chokes on <code class="code">EM_SPARC32PLUS</code>
or <code class="code">EM_SPARCV9</code> executables.
</p>
</dd>
<dt><code class="code">vect_cmdline_needed</code></dt>
<dd><p>Target requires a command line argument to enable a SIMD instruction set.
</p>
</dd>
<dt><code class="code">xorsign</code></dt>
<dd><p>Target supports the xorsign optab expansion.
</p>
</dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Environment-attributes">
<h4 class="subsubsection"><span>7.2.3.14 Environment attributes<a class="copiable-link" href="#Environment-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">c</code></dt>
<dd><p>The language for the compiler under test is C.
</p>
</dd>
<dt><code class="code">c++</code></dt>
<dd><p>The language for the compiler under test is C++.
</p>
</dd>
<dt><code class="code">c99_runtime</code></dt>
<dd><p>Target provides a full C99 runtime.
</p>
</dd>
<dt><code class="code">correct_iso_cpp_string_wchar_protos</code></dt>
<dd><p>Target <code class="code">string.h</code> and <code class="code">wchar.h</code> headers provide C++ required
overloads for <code class="code">strchr</code> etc. functions.
</p>
</dd>
<dt><code class="code">d_runtime</code></dt>
<dd><p>Target provides the D runtime.
</p>
</dd>
<dt><code class="code">d_runtime_has_std_library</code></dt>
<dd><p>Target provides the D standard library (Phobos).
</p>
</dd>
<dt><code class="code">dummy_wcsftime</code></dt>
<dd><p>Target uses a dummy <code class="code">wcsftime</code> function that always returns zero.
</p>
</dd>
<dt><code class="code">fd_truncate</code></dt>
<dd><p>Target can truncate a file from a file descriptor, as used by
<samp class="file">libgfortran/io/unix.c:fd_truncate</samp>; i.e. <code class="code">ftruncate</code> or
<code class="code">chsize</code>.
</p>
</dd>
<dt><code class="code">fenv</code></dt>
<dd><p>Target provides <samp class="file">fenv.h</samp> include file.
</p>
</dd>
<dt><code class="code">fenv_exceptions</code></dt>
<dd><p>Target supports <samp class="file">fenv.h</samp> with all the standard IEEE exceptions
and floating-point exceptions are raised by arithmetic operations.
</p>
</dd>
<dt><code class="code">fenv_exceptions_dfp</code></dt>
<dd><p>Target supports <samp class="file">fenv.h</samp> with all the standard IEEE exceptions
and floating-point exceptions are raised by arithmetic operations for
decimal floating point.
</p>
</dd>
<dt><code class="code">fileio</code></dt>
<dd><p>Target offers such file I/O library functions as <code class="code">fopen</code>,
<code class="code">fclose</code>, <code class="code">tmpnam</code>, and <code class="code">remove</code>.  This is a link-time
requirement for the presence of the functions in the library; even if
they fail at runtime, the requirement is still regarded as satisfied.
</p>
</dd>
<dt><code class="code">freestanding</code></dt>
<dd><p>Target is &lsquo;<samp class="samp">freestanding</samp>&rsquo; as defined in section 4 of the C99 standard.
Effectively, it is a target which supports no extra headers or libraries
other than what is considered essential.
</p>
</dd>
<dt><code class="code">gettimeofday</code></dt>
<dd><p>Target supports <code class="code">gettimeofday</code>.
</p>
</dd>
<dt><code class="code">init_priority</code></dt>
<dd><p>Target supports constructors with initialization priority arguments.
</p>
</dd>
<dt><code class="code">inttypes_types</code></dt>
<dd><p>Target has the basic signed and unsigned types in <code class="code">inttypes.h</code>.
This is for tests that GCC&rsquo;s notions of these types agree with those
in the header, as some systems have only <code class="code">inttypes.h</code>.
</p>
</dd>
<dt><code class="code">lax_strtofp</code></dt>
<dd><p>Target might have errors of a few ULP in string to floating-point
conversion functions and overflow is not always detected correctly by
those functions.
</p>
</dd>
<dt><code class="code">mempcpy</code></dt>
<dd><p>Target provides <code class="code">mempcpy</code> function.
</p>
</dd>
<dt><code class="code">mmap</code></dt>
<dd><p>Target supports <code class="code">mmap</code>.
</p>
</dd>
<dt><code class="code">newlib</code></dt>
<dd><p>Target supports Newlib.
</p>
</dd>
<dt><code class="code">newlib_nano_io</code></dt>
<dd><p>GCC was configured with <code class="code">--enable-newlib-nano-formatted-io</code>, which reduces
the code size of Newlib formatted I/O functions.
</p>
</dd>
<dt><code class="code">posix_memalign</code></dt>
<dd><p>Target supports <code class="code">posix_memalign</code>.
</p>
</dd>
<dt><code class="code">pow10</code></dt>
<dd><p>Target provides <code class="code">pow10</code> function.
</p>
</dd>
<dt><code class="code">pthread</code></dt>
<dd><p>Target can compile using <code class="code">pthread.h</code> with no errors or warnings.
</p>
</dd>
<dt><code class="code">pthread_h</code></dt>
<dd><p>Target has <code class="code">pthread.h</code>.
</p>
</dd>
<dt><code class="code">sockets</code></dt>
<dd><p>Target can compile using <code class="code">sys/socket.h</code> with no errors or warnings.
</p>
</dd>
<dt><code class="code">run_expensive_tests</code></dt>
<dd><p>Expensive testcases (usually those that consume excessive amounts of CPU
time) should be run on this target.  This can be enabled by setting the
<code class="env">GCC_TEST_RUN_EXPENSIVE</code> environment variable to a non-empty string.
</p>
</dd>
<dt><code class="code">simulator</code></dt>
<dd><p>Test system runs executables on a simulator (i.e. slowly) rather than
hardware (i.e. fast).
</p>
</dd>
<dt><code class="code">signal</code></dt>
<dd><p>Target has <code class="code">signal.h</code>.
</p>
</dd>
<dt><code class="code">stabs</code></dt>
<dd><p>Target supports the stabs debugging format.
</p>
</dd>
<dt><code class="code">stdint_types</code></dt>
<dd><p>Target has the basic signed and unsigned C types in <code class="code">stdint.h</code>.
This will be obsolete when GCC ensures a working <code class="code">stdint.h</code> for
all targets.
</p>
</dd>
<dt><code class="code">stdint_types_mbig_endian</code></dt>
<dd><p>Target accepts the option <samp class="option">-mbig-endian</samp> and <code class="code">stdint.h</code>
can be included without error when <samp class="option">-mbig-endian</samp> is passed.
</p>
</dd>
<dt><code class="code">stpcpy</code></dt>
<dd><p>Target provides <code class="code">stpcpy</code> function.
</p>
</dd>
<dt><code class="code">sysconf</code></dt>
<dd><p>Target supports <code class="code">sysconf</code>.
</p>
</dd>
<dt><code class="code">trampolines</code></dt>
<dd><p>Target supports trampolines.
</p>
</dd>
<dt><code class="code">two_plus_gigs</code></dt>
<dd><p>Target supports linking programs with 2+GiB of data.
</p>
</dd>
<dt><code class="code">uclibc</code></dt>
<dd><p>Target supports uClibc.
</p>
</dd>
<dt><code class="code">unwrapped</code></dt>
<dd><p>Target does not use a status wrapper.
</p>
</dd>
<dt><code class="code">vxworks_kernel</code></dt>
<dd><p>Target is a VxWorks kernel.
</p>
</dd>
<dt><code class="code">vxworks_rtp</code></dt>
<dd><p>Target is a VxWorks RTP.
</p>
</dd>
<dt><code class="code">wchar</code></dt>
<dd><p>Target supports wide characters.
</p>
</dd>
<dt><code class="code">weak_undefined</code></dt>
<dd><p>Target supports weak undefined symbols
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Other-attributes">
<h4 class="subsubsection"><span>7.2.3.15 Other attributes<a class="copiable-link" href="#Other-attributes"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">R_flag_in_section</code></dt>
<dd><p>Target supports the &rsquo;R&rsquo; flag in .section directive in assembly inputs.
</p>
</dd>
<dt><code class="code">automatic_stack_alignment</code></dt>
<dd><p>Target supports automatic stack alignment.
</p>
</dd>
<dt><code class="code">branch_cost</code></dt>
<dd><p>Target supports <samp class="option">-branch-cost=N</samp>.
</p>
</dd>
<dt><code class="code">const_volatile_readonly_section</code></dt>
<dd><p>Target places const volatile variables in readonly sections.
</p>
</dd>
<dt><code class="code">cxa_atexit</code></dt>
<dd><p>Target uses <code class="code">__cxa_atexit</code>.
</p>
</dd>
<dt><code class="code">default_packed</code></dt>
<dd><a class="anchor" id="default_005fpacked"></a><p>Target has packed layout of structure members by default.
</p>
</dd>
<dt><code class="code">exceptions</code></dt>
<dd><p>Target supports exceptions.
</p>
</dd>
<dt><code class="code">exceptions_enabled</code></dt>
<dd><p>Target supports exceptions and they are enabled in the current
testing configuration.
</p>
</dd>
<dt><code class="code">fgraphite</code></dt>
<dd><p>Target supports Graphite optimizations.
</p>
</dd>
<dt><code class="code">fixed_point</code></dt>
<dd><p>Target supports fixed-point extension to C.
</p>
</dd>
<dt><code class="code">fopenacc</code></dt>
<dd><p>Target supports OpenACC via <samp class="option">-fopenacc</samp>.
</p>
</dd>
<dt><code class="code">fopenmp</code></dt>
<dd><p>Target supports OpenMP via <samp class="option">-fopenmp</samp>.
</p>
</dd>
<dt><code class="code">fpic</code></dt>
<dd><p>Target supports <samp class="option">-fpic</samp> and <samp class="option">-fPIC</samp>.
</p>
</dd>
<dt><code class="code">freorder</code></dt>
<dd><p>Target supports <samp class="option">-freorder-blocks-and-partition</samp>.
</p>
</dd>
<dt><code class="code">fstack_protector</code></dt>
<dd><p>Target supports <samp class="option">-fstack-protector</samp>.
</p>
</dd>
<dt><code class="code">gas</code></dt>
<dd><p>Target uses GNU <code class="command">as</code>.
</p>
</dd>
<dt><code class="code">gc_sections</code></dt>
<dd><p>Target supports <samp class="option">--gc-sections</samp>.
</p>
</dd>
<dt><code class="code">gld</code></dt>
<dd><p>Target uses GNU <code class="command">ld</code>.
</p>
</dd>
<dt><code class="code">keeps_null_pointer_checks</code></dt>
<dd><p>Target keeps null pointer checks, either due to the use of
<samp class="option">-fno-delete-null-pointer-checks</samp> or hardwired into the target.
</p>
</dd>
<dt><code class="code">llvm_binutils</code></dt>
<dd><p>Target is using an LLVM assembler and/or linker, instead of GNU Binutils.
</p>
</dd>
<dt><code class="code">lra</code></dt>
<dd><p>Target supports local register allocator (LRA).
</p>
</dd>
<dt><code class="code">lto</code></dt>
<dd><p>Compiler has been configured to support link-time optimization (LTO).
</p>
</dd>
<dt><code class="code">lto_incremental</code></dt>
<dd><p>Compiler and linker support link-time optimization relocatable linking
with <samp class="option">-r</samp> and <samp class="option">-flto</samp> options.
</p>
</dd>
<dt><code class="code">naked_functions</code></dt>
<dd><p>Target supports the <code class="code">naked</code> function attribute.
</p>
</dd>
<dt><code class="code">named_sections</code></dt>
<dd><p>Target supports named sections.
</p>
</dd>
<dt><code class="code">natural_alignment_32</code></dt>
<dd><p>Target uses natural alignment (aligned to type size) for types of
32 bits or less.
</p>
</dd>
<dt><code class="code">tail_call</code></dt>
<dd><p>Target supports tail-call optimizations.
</p>
</dd>
<dt><code class="code">target_natural_alignment_64</code></dt>
<dd><p>Target uses natural alignment (aligned to type size) for types of
64 bits or less.
</p>
</dd>
<dt><code class="code">no_alignment_constraints</code></dt>
<dd><p>Target defines __BIGGEST_ALIGNMENT__=1.  Hence target imposes
no alignment constraints.  This is similar, but not necessarily
the same as <a class="ref" href="#default_005fpacked">default_packed</a>.  Although <code class="code">BIGGEST_FIELD_ALIGNMENT</code>
defaults to <code class="code">BIGGEST_ALIGNMENT</code> for most targets, it is possible
for a target to set those two with different values and have different
alignment constraints for aggregate and non-aggregate types.
</p>
</dd>
<dt><code class="code">noinit</code></dt>
<dd><p>Target supports the <code class="code">noinit</code> variable attribute.
</p>
</dd>
<dt><code class="code">nonpic</code></dt>
<dd><p>Target does not generate PIC by default.
</p>
</dd>
<dt><code class="code">o_flag_in_section</code></dt>
<dd><p>Target supports the &rsquo;o&rsquo; flag in .section directive in assembly inputs.
</p>
</dd>
<dt><code class="code">offload_gcn</code></dt>
<dd><p>Target has been configured for OpenACC/OpenMP offloading on AMD GCN.
</p>
</dd>
<dt><code class="code">persistent</code></dt>
<dd><p>Target supports the <code class="code">persistent</code> variable attribute.
</p>
</dd>
<dt><code class="code">pie_enabled</code></dt>
<dd><p>Target generates PIE by default.
</p>
</dd>
<dt><code class="code">pcc_bitfield_type_matters</code></dt>
<dd><p>Target defines <code class="code">PCC_BITFIELD_TYPE_MATTERS</code>.
</p>
</dd>
<dt><code class="code">pe_aligned_commons</code></dt>
<dd><p>Target supports <samp class="option">-mpe-aligned-commons</samp>.
</p>
</dd>
<dt><code class="code">pie</code></dt>
<dd><p>Target supports <samp class="option">-pie</samp>, <samp class="option">-fpie</samp> and <samp class="option">-fPIE</samp>.
</p>
</dd>
<dt><code class="code">rdynamic</code></dt>
<dd><p>Target supports <samp class="option">-rdynamic</samp>.
</p>
</dd>
<dt><code class="code">scalar_all_fma</code></dt>
<dd><p>Target supports all four fused multiply-add optabs for both <code class="code">float</code>
and <code class="code">double</code>.  These optabs are: <code class="code">fma_optab</code>, <code class="code">fms_optab</code>,
<code class="code">fnma_optab</code> and <code class="code">fnms_optab</code>.
</p>
</dd>
<dt><code class="code">section_anchors</code></dt>
<dd><p>Target supports section anchors.
</p>
</dd>
<dt><code class="code">short_enums</code></dt>
<dd><p>Target defaults to short enums.
</p>
</dd>
<dt><code class="code">stack_size</code></dt>
<dd><a class="anchor" id="stack_005fsize_005fet"></a><p>Target has limited stack size.  The stack size limit can be obtained using the
STACK_SIZE macro defined by <a class="ref" href="Add-Options.html#stack_005fsize_005fao"><code class="code">dg-add-options</code> feature
<code class="code">stack_size</code></a>.
</p>
</dd>
<dt><code class="code">static</code></dt>
<dd><p>Target supports <samp class="option">-static</samp>.
</p>
</dd>
<dt><code class="code">static_libgfortran</code></dt>
<dd><p>Target supports statically linking &lsquo;<samp class="samp">libgfortran</samp>&rsquo;.
</p>
</dd>
<dt><code class="code">string_merging</code></dt>
<dd><p>Target supports merging string constants at link time.
</p>
</dd>
<dt><code class="code">ucn</code></dt>
<dd><p>Target supports compiling and assembling UCN.
</p>
</dd>
<dt><code class="code">ucn_nocache</code></dt>
<dd><p>Including the options used to compile this particular test, the
target supports compiling and assembling UCN.
</p>
</dd>
<dt><code class="code">unaligned_stack</code></dt>
<dd><p>Target does not guarantee that its <code class="code">STACK_BOUNDARY</code> is greater than
or equal to the required vector alignment.
</p>
</dd>
<dt><code class="code">vector_alignment_reachable</code></dt>
<dd><p>Vector alignment is reachable for types of 32 bits or less.
</p>
</dd>
<dt><code class="code">vector_alignment_reachable_for_64bit</code></dt>
<dd><p>Vector alignment is reachable for types of 64 bits or less.
</p>
</dd>
<dt><code class="code">vma_equals_lma</code></dt>
<dd><p>Target generates executable with VMA equal to LMA for .data section.
</p>
</dd>
<dt><code class="code">wchar_t_char16_t_compatible</code></dt>
<dd><p>Target supports <code class="code">wchar_t</code> that is compatible with <code class="code">char16_t</code>.
</p>
</dd>
<dt><code class="code">wchar_t_char32_t_compatible</code></dt>
<dd><p>Target supports <code class="code">wchar_t</code> that is compatible with <code class="code">char32_t</code>.
</p>
</dd>
<dt><code class="code">comdat_group</code></dt>
<dd><p>Target uses comdat groups.
</p>
</dd>
<dt><code class="code">indirect_calls</code></dt>
<dd><p>Target supports indirect calls, i.e. calls where the target is not
constant.
</p>
</dd>
<dt><code class="code">lgccjit</code></dt>
<dd><p>Target supports -lgccjit, i.e. libgccjit.so can be linked into jit tests.
</p>
</dd>
<dt><code class="code">__OPTIMIZE__</code></dt>
<dd><p>Optimizations are enabled (<code class="code">__OPTIMIZE__</code>) per the current
compiler flags.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Local-to-tests-in-gcc_002etarget_002fi386">
<h4 class="subsubsection"><span>7.2.3.16 Local to tests in <code class="code">gcc.target/i386</code><a class="copiable-link" href="#Local-to-tests-in-gcc_002etarget_002fi386"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">3dnow</code></dt>
<dd><p>Target supports compiling <code class="code">3dnow</code> instructions.
</p>
</dd>
<dt><code class="code">aes</code></dt>
<dd><p>Target supports compiling <code class="code">aes</code> instructions.
</p>
</dd>
<dt><code class="code">fma4</code></dt>
<dd><p>Target supports compiling <code class="code">fma4</code> instructions.
</p>
</dd>
<dt><code class="code">mfentry</code></dt>
<dd><p>Target supports the <code class="code">-mfentry</code> option that alters the
position of profiling calls such that they precede the prologue.
</p>
</dd>
<dt><code class="code">ms_hook_prologue</code></dt>
<dd><p>Target supports attribute <code class="code">ms_hook_prologue</code>.
</p>
</dd>
<dt><code class="code">pclmul</code></dt>
<dd><p>Target supports compiling <code class="code">pclmul</code> instructions.
</p>
</dd>
<dt><code class="code">sse3</code></dt>
<dd><p>Target supports compiling <code class="code">sse3</code> instructions.
</p>
</dd>
<dt><code class="code">sse4</code></dt>
<dd><p>Target supports compiling <code class="code">sse4</code> instructions.
</p>
</dd>
<dt><code class="code">sse4a</code></dt>
<dd><p>Target supports compiling <code class="code">sse4a</code> instructions.
</p>
</dd>
<dt><code class="code">ssse3</code></dt>
<dd><p>Target supports compiling <code class="code">ssse3</code> instructions.
</p>
</dd>
<dt><code class="code">vaes</code></dt>
<dd><p>Target supports compiling <code class="code">vaes</code> instructions.
</p>
</dd>
<dt><code class="code">vpclmul</code></dt>
<dd><p>Target supports compiling <code class="code">vpclmul</code> instructions.
</p>
</dd>
<dt><code class="code">xop</code></dt>
<dd><p>Target supports compiling <code class="code">xop</code> instructions.
</p></dd>
</dl>

</div>
<div class="subsubsection-level-extent" id="Local-to-tests-in-gcc_002etest_002dframework">
<h4 class="subsubsection"><span>7.2.3.17 Local to tests in <code class="code">gcc.test-framework</code><a class="copiable-link" href="#Local-to-tests-in-gcc_002etest_002dframework"> &para;</a></span></h4>

<dl class="table">
<dt><code class="code">no</code></dt>
<dd><p>Always returns 0.
</p>
</dd>
<dt><code class="code">yes</code></dt>
<dd><p>Always returns 1.
</p></dd>
</dl>

</div>
</div>
<hr>
<div class="nav-panel">
<p>
Next: <a href="Add-Options.html">Features for <code class="code">dg-add-options</code></a>, Previous: <a href="Selectors.html">Selecting targets to which a test applies</a>, Up: <a href="Test-Directives.html">Directives used within DejaGnu tests</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html" title="Index" rel="index">Index</a>]</p>
</div>



</body>
</html>
